MIT 6.004 - Computation Structures: Digital Logic, Processor Pipelines & RISC-V Flashcards

Question 1

What does CMOS stand for, and what are its primary components?

Accepted Answer

`CMOS` stands for Complementary Metal-Oxide-Semiconductor. It uses both P-type (`PMOS`) and N-type (`NMOS`) transistors to construct logic gates, known for low power consumption.

Question 2

How does a basic CMOS inverter operate?

Accepted Answer

A `CMOS` inverter consists of a `PMOS` transistor and an `NMOS` transistor connected in series between power (`VDD`) and ground (`GND`). When the input is high, the `NMOS` turns on and `PMOS` turns off, pulling the output low. When the input is low, the `PMOS` turns on and `NMOS` turns off, pulling the output high.

Question 3

Define `propagation delay` ($t_{PD}$) in digital circuits.

Accepted Answer

The maximum time it takes for the output of a logic gate or circuit to respond to a change in its input. It's the time from when an input changes until the output settles to its new stable value.

Question 4

Define `contamination delay` ($t_{CD}$) in digital circuits.

Accepted Answer

The minimum time it takes for the output of a logic gate or circuit to *start* responding to a change in its input. It's the earliest time an output might change after an input changes.

Question 5

What is Sequential Logic?

Accepted Answer

Digital logic circuits whose output depends not only on the current inputs but also on the sequence of past inputs, meaning they have memory. Examples include flip-flops, registers, and counters.

Question 6

What is a D-type Flip-Flop?

Accepted Answer

A fundamental 1-bit memory element in sequential logic. It stores the value present at its `D` (data) input when triggered by a clock edge, holding that value until the next active clock edge.

Question 7

What is a Finite State Machine (FSM)?

Accepted Answer

A mathematical model of computation used to design sequential logic. An `FSM` can be in exactly one of a finite number of states at any given time, and transitions between states based on inputs and a clock.

Question 8

Differentiate between Mealy and Moore FSMs.

Accepted Answer

*   **Mealy FSM:** Outputs depend on both the current state *and* the current inputs.
*   **Moore FSM:** Outputs depend *only* on the current state.

Question 9

List the 5 stages of a classic RISC CPU pipeline.

Accepted Answer

1.  `IF` (Instruction Fetch)
2.  `ID` (Instruction Decode/Register Fetch)
3.  `EX` (Execute)
4.  `MEM` (Memory Access)
5.  `WB` (Write Back)

Question 10

What is a Data Hazard in a CPU pipeline?

Accepted Answer

Occurs when an instruction tries to read a register before a preceding instruction has written to it, leading to incorrect data being used.

Question 11

How are Data Hazards typically resolved in a pipeline?

Accepted Answer

The most common technique is `forwarding` (or `bypassing`), where the result of an instruction is sent directly from an internal pipeline register to the input of a later instruction that needs it, rather than waiting for it to be written back to the register file. Stalling is another, less efficient, method.

Question 12

What is a Control Hazard (or Branch Hazard) in a CPU pipeline?

Accepted Answer

Occurs when the pipeline fetches instructions sequentially, but a branch instruction changes the program counter, making the fetched instructions incorrect. The pipeline doesn't know the next instruction until the branch condition is evaluated.

Question 13

What is Combinational Logic?

Accepted Answer

Digital logic circuits whose output is a pure function of its current inputs, with no memory or feedback. Examples include adders, multiplexers, and decoders.

Question 14

Explain the concept of a Logic Gate.

Accepted Answer

An elementary building block of digital circuits that implements a basic Boolean function (e.g., `AND`, `OR`, `NOT`, `XOR`, `NAND`, `NOR`).

Question 15

State De Morgan's Laws in Boolean Algebra.

Accepted Answer

1. $\overline{A \cdot B} = \overline{A} + \overline{B}$
2. $\overline{A + B} = \overline{A} \cdot \overline{B}$
These laws describe how to convert between `AND` and `OR` operations when negating expressions.

Question 16

What is a Multiplexer (Mux)?

Accepted Answer

A combinational circuit that selects one of several input signals and forwards the selected input into a single output line. The selection is controlled by a set of select lines.

Question 17

How are Control Hazards typically resolved?

Accepted Answer

Common techniques include:
*   `Stalling`: Inserting `NOP` (No Operation) instructions until the branch target is known.
*   `Branch Prediction`: Guessing the outcome of a branch and speculatively fetching instructions. If the prediction is wrong, the pipeline must flush and restart.
*   `Delayed Branch`: Reordering instructions so that an instruction after the branch is always executed, regardless of the branch outcome.

Question 18

What is RISC-V?

Accepted Answer

An open-source Instruction Set Architecture (`ISA`) based on `RISC` (Reduced Instruction Set Computer) principles. It's designed to be modular, extensible, and free to use, making it popular for research and custom hardware.

Question 19

What is Cache Memory?

Accepted Answer

A small, fast memory located close to the CPU that stores copies of data from main memory that are likely to be accessed soon. It exploits the principle of locality to reduce average memory access time.

Question 20

Explain the principle of Locality of Reference in caching.

Accepted Answer

The tendency for a processor to access the same set of memory locations repetitively over a short period. It has two forms:
*   `Temporal Locality`: Recently accessed items are likely to be accessed again soon.
*   `Spatial Locality`: Items whose addresses are near one another tend to be referenced close in time.

Question 21

Describe Direct-Mapped Cache.

Accepted Answer

A cache organization where each block from main memory can only be placed in one specific location (cache line) in the cache. This location is determined by a direct mapping function, typically using a portion of the memory address (the index).

Question 22

Describe Set-Associative Cache.

Accepted Answer

A cache organization where each block from main memory can be placed in any location within a specific "set" of cache lines. The memory address is divided into tag, set index, and block offset. It offers a compromise between direct-mapped and fully associative caches.

Question 23

Describe Fully Associative Cache.

Accepted Answer

A cache organization where any block from main memory can be placed in *any* cache line. This offers the most flexibility but requires complex hardware for searching all cache lines simultaneously, making it expensive and typically used only for small caches (e.g., TLBs).

MIT 6.004 - Computation Structures: Digital Logic, Processor Pipelines & RISC-V

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