MIT 6.004 - Computation Structures & Digital Logic Design

A CMOS inverter consists of a PMOS pull-up network connected to $V_{DD}$ and an NMOS pull-down network connected to $GND$. When input $V_{IN}=1$ (high), NMOS conducts and PMOS turns off, pulling $V_{OUT}=0$. When $V_{IN}=0$ (low), PMOS conducts and NMOS turns off, pulling $V_{OUT}=1$.

• Propagation Delay ($t_{pd}$): The maximum time from an input change until the output settles to its final valid value.
• Contamination Delay ($t_{cd}$): The minimum time from an input change until the output begins to change from its initial valid value.

• Setup Time ($t_{setup}$): Minimum duration data input must remain stable before the active clock edge.
• Hold Time ($t_{hold}$): Minimum duration data input must remain stable after the active clock edge to ensure valid state capture.

To avoid setup time violations in a register-to-register path, the clock period $t_{CLK}$ must satisfy:
$$t_{CLK}\ge t_{pd,FF}+t_{pd,comb}+t_{setup}$$
Where $t_{pd,FF}$ is flip-flop propagation delay and $t_{pd,comb}$ is maximum combinational logic propagation delay.

To avoid hold time violations in a register-to-register path, the minimum path delay must satisfy:
$$t_{cd,FF}+t_{cd,comb}\ge t_{hold}$$
Note: Hold time constraints are independent of the clock period $t_{CLK}$ and are fixed by adding buffer delays ($t_{cd,comb}$).

A digital signaling standard specifying that if inputs satisfy valid logic voltage thresholds ($V_{IL}$ or $V_{IH}$), the circuit output will strictly adhere to valid logic thresholds ($V_{OL}$ or $V_{OH}$), providing noise margin:
$$NoiseMargi{n}_{High}=V_{OH}-V_{IH}$$
$$NoiseMargi{n}_{Low}=V_{IL}-V_{OL}$$

Fundamental rules in Boolean algebra used for logic minimization and NAND/NOR conversions:
1. $\overline{A\cdot B}=\overline{A}+\overline{B}$
2. $\overline{A+B}=\overline{A}\cdot \overline{B}$

A circuit is strictly combinational if:
1. Every circuit element is combinational.
2. Every node is connected to a single output or supply rail ($V_{DD}/GND$).
3. The circuit contains no directed cycles (no feedback paths).